a) Field of the Invention
The present invention relates to a semiconductor device of a multi-layer interconnection structure and a method for manufacturing the same, and in particular, to a structure of an interlevel dielectric layer formed between interconnect layers.
b) Description of the Related Art
With a miniaturization of semiconductor elements, it is essential to employ finer interconnect patterns in a semiconductor device of a multi-layer interconnection structure. To provide an interlayer insulating film for a semiconductor device which includes multilayer interconnect patterns, an insulating film made of silicon oxide which has a reduced dielectric constant and a stabilized quality is dominantly used for the purpose of reducing parasitic capacitances between upper (or overlying) interconnect layer and a lower (or underlying) interconnect layer as well as between interconnects in the same layer.
The width of interconnects and the spacing between the interconnects of a lower layer interconnect pattern is especially reduced with the miniaturization of the semiconductor devices. However, in order to avoid an increase in the interconnect resistance, it is necessary to secure a sufficient cross-sectional area for the interconnects. Accordingly, there results an increase in the aspect ratio of the interconnect itself (ratio of thickness to width of the interconnect) and an inter-interconnect aspect ratio (ratio of interconnect thickness to spacing between interconnects). In the latter respect, it will be necessary that an interlayer insulating film be provided to sufficiently fill the spaces between the underlying interconnects.
At the region where there is a significant physical step or level difference on the surface of the interlayer insulating film, insufficient focus margin will results in the photolithography and cannot therefore provide a fine resist pattern during the formation of a interconnect pattern in an overlying interconnect layer. Even after the fine resist pattern is formed, the significant step may cause a breakage in the overlying interconnects and also causes an etching residue of interconnect material to be left in the step region. Accordingly, it is required that the surface of the interlayer insulating film be smooth. Where the underlying interconnection is made of aluminum or an aluminum based alloy (referred to as simply aluminum hereinafter) in particular, a restriction is imposed on the interlayer insulating film that the insulating film be formed at a temperature which is 450.degree. C. at most.
A technique of forming an interlayer insulating film in a fine multilayer interconnect structure made of aluminum is described, for example, in Japanese Patent Publication No. JP-B-1994-69038, which will be described below with reference to drawings as a first prior art.
FIGS. 1A to 1D show cross-sections of a semiconductor device described in the publication as mentioned above in consecutive steps of manufacturing the same. Referring first to FIG. 1A, formed on the main surface of a silicon substrate 101 is a thick insulating film 102, on which a first layer interconnect pattern made of aluminum and including interconnects 103a, 103b, 103c and 103d are formed.
Subsequently, a first interlayer insulating film 104 made of phospho-silicate glass (PSG) is deposited by a chemical vapor deposition (CVD) process so as to cover the first layer interconnects 103a, 103b, 103c and 103d and the thick insulating film 102. If the first layer interconnects are formed in a fine pattern and have a high aspect ratio, undesirable voids 105a and 105b will be formed in the insulating film, as shown in FIG. 1A.
Then, a liquid glass is spin-coated onto the first PSG film 104, and subjected to a heat treatment at a temperature of about 450.degree. C. During the heat treatment, the liquid glass becomes solidified, forming a spin-on glass film 106 on the first PSG film 104 to form a structure shown in FIG. 1B.
Subsequently, the spin-on glass film 106 and a top portion of the first PSG film 104 are etched back by a dry etching process, as shown in FIG. 1C. The reactive gas used for the dry etching process contains a mixture of CF.sub.4 and O.sub.2. Since the voids 105a and 105b have been formed in the first PSG film 104, the first PSG film 104 is etched until these voids 105a and 105b are exposed during the etch-back step. As a result of the etch-back step, the first PSG film 104 which has exhibited a considerable degree of unevenness at the step of FIG. 1B is smoothed as shown in FIG. 1C.
A second PSG film 107 is then deposited on the smoothed first PSG film 104, as shown in FIG. 1D. In this manner, an interlevel dielectric layer including the first PSG film 104 and second PSG film 107 is formed on the first layer interconnects 103a, 103b, 103c and 103d.
Subsequently, a second layer interconnect pattern, which maybe made of aluminum, is formed on the interlevel dielectric layer, thereby achieving a two-layer interconnection structure.
Another example of a method for forming an interlevel dielectric layer in a fine multilayer interconnection structure is described in Japanese Patent Publication No. JP-A-1993-206,282, which will now be described as a second prior art.
FIGS. 2A to 2D are cross-sections of another semiconductor device in consecutive steps of the second prior art method as mentioned above. Referring to FIG. 2A, formed on a silicon substrate 201 is a thick insulating film 202 by a CVD process, on which a first layer interconnects 203a, 203b, 203c and 203d, which may be made of aluminum, are formed.
A first silicon oxide film is deposited on the first layer interconnects 203a, 203b, 203c and 203d and the thick insulating film 202 by using a plasma enhanced CVD (PECVD) process to provide a PECVD silicon oxide film 204, as shown in FIG. 2A. The first silicon oxide film 204 has a reduced thickness which is just sufficient to cover the surfaces of the first layer interconnects 203a, 203b, 203c and 203d.
A second silicon oxide film 205 is then formed, as shown in FIG. 2B, by an atmospheric pressure CVD process using as a reactive gas a mixture of TEOS (tetraethoxysilane: Si(OC.sub.2 H.sub.5).sub.4) and O.sub.2 gas containing O.sub.3.
Subsequently, a liquid organic silica having a main constituent represented by CH.sub.3 Si(OH).sub.3 is applied by a spin-coating technique onto the second silicon oxide film 205, and subjected to a heat-treatment for an hour at a temperature of about 300.degree. C. in a nitrogen atmosphere. In this manner, an organic silica film 206 is formed on the second silicon oxide film 205, as shown in FIG. 2C. Subsequently, the organic silica film 206 and a top portion of the second silicon oxide film 205 are etched back by a dry etching technique using CF.sub.4 gas. The etch-back step completely removes the organic silica film 206 to flatten the second silicon oxide film 205.
Then follows a deposition of a third silicon oxide film, if necessary, on the flattened second silicon oxide film 205. It is to be noted that the third silicon oxide film is deposited by a PECVD process. An interlevel dielectric layer is thus formed. Subsequently, via-holes which reach the underlying first layer interconnects are formed in the interlevel dielectric layer, and a second layer interconnect pattern made of aluminum is then formed, thereby forming a two-layer interconnection structure.
The first prior art has a problem in that voids 105a and 105b are frequently formed in the insulating film at the spaces between the first layer interconnects, especially when the first PSG film 104 is thick, as shown in FIG. 1A. These voids remain in the interlevel dielectric layer even after the etch-back steps for flattening and the deposition of the second PSG film. Such a problem will be serious as the width of the first layer interconnects and the spacing therebetween are reduced to increase the inter-interconnect aspect ratio, which are generally accompanied by the miniaturization of the semiconductor elements.
Further, the PSG film 104 formed in the manner mentioned above has uneven surface to leave a residual metal of the overlying interconnect pattern after the etching thereof. This is because the PSG film in general has a poor step coverage, and, in particular, when the inter-interconnect aspect ratio is equal to or greater than unit and the spacing between interconnects is equal to or less than 1 micron (.mu.m), the PSG film will not be deposited on the side-walls of the interconnects.
The second problem involved in the first prior art necessitates that the first PSG film 104 be deposited to a sufficient thickness even though voids in the insulating film may then be formed at spaces between the underlying interconnects as mentioned before. We analyzed the cause as follows: to assure a sufficient smoothness and flatness, it is desirable to select a ratio at unit or close to unit between the etch rate for the etch-back of the spin-on glass film 106 and the etch rate for the first PSG film 104. However, as a result of characteristics of the liquid glass during the spin-coating step, the spin-on glass film 106 is little formed on top of the isolated underlying interconnects, such as designated by numeral 103a. As a consequence, a portion of the first PSG film 104 overlying the isolated interconnect 103a is exposed during the initial phase of the etch-back step, and upon completion of the etch-back, the portion of the first PSG film is little left on the isolated interconnect 103a. For this reason, a sufficient thickness of the first PSG film 104 is required.
In addition, when the diameter of the via-hole is small, it will be necessary to remove the spin-on glass film 106 completely from the top surface of the interconnects by the etch-back step. This results from the following reason.
Specifically, if the spin-on glass film 106 is formed as an inorganic silica film, and if the inorganic silica film is exposed on the sidewall of the via-hole during the etching step for the via-hole, moisture will desorp from the inorganic silica film during the formation of the overlying interconnection layer, thereby raising the contact resistance between the overlying interconnects and the underlying interconnects. In particular, if the diameter of the via-hole is equal to or less than 1 .mu.m, the problem of the increased contact resistance will be serious.
On the other hand, if the spin-on glass film 106 is formed as an organic silica film, it is necessary to provide an ashing treatment with an oxygen plasma in order to remove the photoresist after the etching step for the via-hole. However, the ashing treatment oxidizes the organic components in the organic silica film, making the spin-on glass film porous or reducing the spin-on glass film in the volume, whereby a desirable configuration of the via-hole will be lost to provide a barrel-shaped via-hole. For these reasons, it is necessary to grow the first PSG film 104 to a sufficient thickness.
In the second prior art, a first problem occurs when voids 207a and 207b are formed in the insulating film 205 at the spaces between underlying interconnects, as shown in FIG. 2B. These voids will be formed in a finer pattern wherein, for example, the spacing between the interconnects is equal to or less than 0.6 .mu.m and the inter-interconnect aspect ratio is equal to or greater than unit.
Generally, the filling capability of the silicon oxide film formed by a CVD process using TEOS gas and O.sub.3 gas to fill spaces between the interconnects is superior to a silicon oxide film deposited by another known technology. However, as the interconnect pat-tern becomes finer, voids are generated in the insulating film even in the technique as used herein.
A second problem involved in the second prior art is that, in the interlayer insulating film formed by the second prior art, the interlayer insulating film has an uneven surface, thereby increasing the possibility that the overlying interconnects may be broken or a residual metal of the overlying interconnects may remain after the etching thereof. This is because the coating capability of the liquid organic silica is not sufficient in case of coating on the second silicon oxide film 205 formed by a mixture of TEOS and O.sub.2 gas containing O.sub.3, providing a non-uniformity of the coat by repelling the liquid organic silica. This problem is also noted with an inorganic silica film.